Hynix H5GQ2H24MFR-T2C BGA

H5GQ2H24MFR-T2C 2.5 GHz BGA Chip

The GDDR5 SGRAM is a high speed dynamic random access memory designed for applications requiring high bandwidth. GDDR5 devices contain the following number of bits: 2Gb has 2,147,483,648 bits and sixteen banks The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high speed operation. The device can be configured to operate in x32 mode or x16 (clamshell) mode. 

Features:

•  Single ended interface for data, address and command
• Quarter data‐rate differential clock inputs CK/CK# for ADR/CMD
• Two half data‐rate differential clock inputs WCK/ WCK#, each associated with two data bytes (DQ, DBI#, EDC)
• Double Data Rate (DDR) data (WCK)
• Single Data Rate (SDR) command (CK)
• Double Data Rate (DDR) addressing (CK)
• 16 internal banks
• Boundary scan function with SEN pin
• 1.6V / 1.5V / 1.35V +/‐ (3%xVDD)V supply for device operation (VDD)
• 1.6V / 1.5V / 1.35V +/‐ (3%xVDDQ)V supply for I/O interface (VDDQ)
• 170 ball BGA package

Datasheet:

https://bit.ly/2qFCyMq